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19-3150; Rev 2; 10/05
10V, Dual, 12-Bit, Serial, Voltage-Output DAC
General Description
The MAX5322 dual, 12-bit, serial-interface, digital-to-analog converter (DAC) provides bipolar 5V to 10V outputs from 12V to 15V analog power-supply voltages, or unipolar 5V to 10V outputs from a single 12V to 15V analog power-supply voltage. The MAX5322 features excellent linearity with both integral nonlinearity (INL) and differential nonlinearity (DNL) guaranteed to 1 LSB (max). The device also features a fast 10s to 0.5 LSB settling time, and a hardware-shutdown feature that reduces current consumption to 2.8A. The output goes to midscale at power-up in bipolar mode (0V), and to zero scale at power-up in unipolar mode (0V). A clear input (CLR) asynchronously clears the DAC register and sets the outputs to 0V. The outputs can be asynchronously updated with the load DAC (LDAC) input. The device features a fast 10MHz SPITM-/QSPITM/MICROWIRETM-compatible serial interface that operates with 3V or 5V logic. Additional features include a serialdata output (DOUT) for daisy chaining and read-back functions. The MAX5322 requires external reference voltages of 2V to 5.25V and is available in a 28-pin SSOP package that operates over the extended (-40C to +85C) temperature range.
Features
Unipolar or Bipolar Output-Voltage Ranges Unipolar: 0 to +2 x VREF (Single or Dual Supply) Bipolar: -2 x VREF to +2 x VREF (Dual Supply) Guaranteed INL 1 LSB (max) Guaranteed Monotonic: DNL 1 LSB (max) 10s Settling Time to 0.5 LSB Low 2.8A Shutdown Current Fast 10MHz SPI-/QSPI-/MICROWIRE-Compatible Serial Interface Power-On Reset Sets DAC Output to 0V Schmitt Trigger Inputs for Direct Optocoupler Interface Serial-Data Output Allows Daisy-Chaining of Devices 28-Pin SSOP (8mm x 10mm)
MAX5322
Applications
Motor Control Industrial Process Controls Industrial Automation Automatic Test Equipment (ATE) Analog I/O Boards Data-Acquisition Systems
PART MAX5322EAI
Ordering Information
TEMP RANGE -40C to +85C PIN-PACKAGE 28 SSOP
Functional Diagram
2R 2R
SW2 REFA LDAC CLR 12 INPUT REGISTERS 12 REFB DIN SCLK CS UNI/BIPA UNI/BIPB SHDN DOUT VCC DGND 16-BIT SHIFT REGISTER 2R SERIAL INTERFACE AND CONTROL 2R 2R 12 DAC REGISTERS SW6 12 12-BIT DAC B SW4 SW5 A3 A4 SGNDA OUTB 2R 12-BIT DAC A SW1 A1 A2 SW3 2R OUTA
DIGITAL POWER
2R
MAX5322
ANALOG POWER
SGNDB VSS VDD AGND
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
10V, Dual, 12-Bit, Serial, Voltage-Output DAC MAX5322
ABSOLUTE MAXIMUM RATINGS
VDD to AGND..........................................................-0.3V to +17V VSS to AGND ..........................................................-17V to +0.3V VDD to VSS ..........................................................................+34V VCC to DGND ...........................................................-0.3V to +6V AGND to DGND.....................................................-0.3V to +0.3V SGND_ to AGND ...................................................-0.3V to +0.3V SCLK, DIN, CS, SHDN, UNI/BIP_, CLR, LDAC, DOUT to DGND ..........................-0.3V to (VCC + 0.3V) OUT_ to AGND.................................(VSS - 0.3V) to (VDD + 0.3V) REF_ to AGND..........................................................-0.3V to +6V Maximum Current into REF_ .............................................10mA Maximum Current into Any Pin Excluding REF_...............50mA Continuous Power Dissipation (TA = +70C) 28-Pin SSOP (derate 9.5mW/C above +70C) ........761.9mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS (DUAL SUPPLY)
(VDD = +15V 5%, VSS = -15V 5%, VCC = +5V 10%, AGND = DGND = SGND_ = 0V, VREF_ = 5V, RLOAD = 2k, CLOAD = 250pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER STATIC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Zero-Scale Error Zero-Scale Temperature Coefficient Gain Error Gain-Error Temperature Coefficient ANALOG OUTPUTS (OUTA, OUTB) Output Voltage Range Resistive Load to GND Capacitive Load to GND DC Output Resistance SGND INPUTS (SGNDA, SGNDB) Input Impedance REFERENCE INPUTS (REFA, REFB) Reference Voltage Input Range Input Resistance Reference Bandwidth RREF Code = 555hex, worst-case code VREF = 200mVP-P + 5VDC 2.00 15 22 200 5.25 V k kHz 92 k RLOAD CLOAD 0.5 (VSS + 1.5V) < VOUT < (VDD - 1.5V) -2 x VREF 2 250 +2 x VREF V k pF N INL DNL Guaranteed monotonic Bipolar, code = 800hex Unipolar, code = 000hex Bipolar Unipolar Bipolar (output unloaded) Unipolar (output unloaded) Bipolar (output unloaded) Unipolar (output unloaded) 2 2 0.9 0.09 2 2 12 1 1 2 2 Bits LSB LSB LSB ppm FSR/C LSB ppm FSR/C SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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10V, Dual, 12-Bit, Serial, Voltage-Output DAC
ELECTRICAL CHARACTERISTICS (DUAL SUPPLY) (continued)
(VDD = +15V 5%, VSS = -15V 5%, VCC = +5V 10%, AGND = DGND = SGND_ = 0V, VREF_ = 5V, RLOAD = 2k, CLOAD = 250pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS +2.7V VCC +3.6V +4.5V VCC +5.5V +2.7V VCC +3.6V +4.5V VCC +5.5V +2.7V VCC +3.6V +4.5V VCC +5.5V 0 all digital inputs VCC, +2.7V VCC +3.6V 0 all digital inputs VCC, +4.5V VCC +5.5V VCC 0.5 0.4 0.1 10 2.5 To 0.5 LSB of full scale, code 000 to code FFF CS = high, fSCLK = 10MHz, VOUT = 0V 10 10 2.5 130 10 10 1 A 1 MIN 0.7 x VCC 2.4 0.8 0.8 TYP MAX UNITS DIGITAL INPUTS (SCLK, DIN, CS, SHDN, UNI/BIPA, UNI/BIPB, CLR, LDAC) Input Voltage High Input Voltage Low Input Capacitance VIH VIL C V V pF
MAX5322
Input Current (Note 1)
DIGITAL OUTPUT (DOUT) Output Voltage High Output Voltage Low Tri-State Leakage Current Tri-State Capacitance DYNAMIC PERFORMANCE Voltage Output Slew Rate Output Settling Time Digital Feedthrough DAC-to-DAC Crosstalk Output-Noise Spectral Density at 10kHz POWER SUPPLIES Positive Analog-Supply Voltage Negative Analog-Supply Voltage Positive Digital-Supply Voltage Positive Analog-Supply Current Negative Analog-Supply Current Digital-Supply Current Power-Supply Rejection Ratio (Note 2) Shutdown Current VDD VSS VCC IDD ISS ICC PSRR Output unloaded, VOUT = 0 Output unloaded, VOUT = 0 All digital inputs = 0 or VCC Positive analog supply Negative analog supply Positive analog supply Negative analog supply Digital supply 0.0006 0.03 2.8 4 4 50 50 10 A 10.80 -10.80 2.7 2.8 -1.5 15.75 -15.75 5.5 8 -8 200 V V V mA mA A LSB/V V/s s nV-s nV-s nV/Hz VOH VOL ISOURCE = 2mA ISINK = 2mA V V A pF
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3
10V, Dual, 12-Bit, Serial, Voltage-Output DAC MAX5322
ELECTRICAL CHARACTERISTICS (SINGLE SUPPLY)
(VDD = +15V 5%, VSS = 0V, VCC = +5V 10%, AGND = DGND = SGND_ = 0V, VREF_ = 5V, RLOAD = 10k, CLOAD = 250pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER STATIC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Unipolar Zero-Scale Error Unipolar Zero-Scale Temperature Coefficient Gain Error Gain-Error Temperature Coefficient ANALOG OUTPUTS (OUTA, OUTB) Output Voltage Range Resistive Load to GND Capacitive Load to GND DC Output Resistance SGND INPUTS (SGNDA, SGNDB) Input Impedance REFERENCE INPUTS (REFA, REFB) Reference Voltage Input Range Input Resistance Reference Input Bandwidth Code = 555hex, worst-case code VREF = 200mVP-P + 5VDC 0.7 x VCC 2.4 0.8 0.8 10 10 1 1 VCC 0.5 0.4 0.1 V pF A 2.00 15 22 150 5.25 V k kHz 92 k RLOAD CLOAD 0.5 0 10 250 +2 x VREF V k pF No load No load 2 0.09 2 N INL DNL (Note 3) Guaranteed monotonic 12 1 1 2 Bits LSB LSB LSB ppm FSR/C LSB ppm FSR/C SYMBOL CONDITIONS MIN TYP MAX UNITS
DIGITAL INPUTS (SCLK, DIN, CS, SHDN, UNI/BIPA, UNI/BIPB, CLR, LDAC) Input Voltage High VIH +2.7V VCC +3.6V +4.5V VCC +5.5V Input Voltage Low Input Capacitance Input Current DIGITAL OUTPUT (DOUT) Output Voltage High Output Voltage Low Tri-State Leakage Current VOH VOL ISOURCE = 2mA ISINK = 2mA V V A VIL CIN IIN +2.7V VCC +3.6V +4.5V VCC +5.5V +2.7V VCC +3.6V +4.5V VCC +5.5V 0 VIN VCC, +2.7V VCC +3.6V 0 VIN VCC, +4.5V VCC +5.5V V
4
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10V, Dual, 12-Bit, Serial, Voltage-Output DAC
ELECTRICAL CHARACTERISTICS (SINGLE SUPPLY) (continued)
(VDD = +15V 5%, VSS = 0V, VCC = +5V 10%, AGND = DGND = SGND_ = 0V, VREF_ = 5V, RLOAD = 10k, CLOAD = 250pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Tri-State Capacitance DYNAMIC PERFORMANCE Voltage Output Slew Rate Output Settling Time Digital Feedthrough DAC-to-DAC Crosstalk Output-Noise Spectral Density at 10kHz POWER SUPPLIES Positive Analog Supply Voltage Negative Analog Supply Voltage Positive Digital Supply Voltage Positive Analog Supply Current Negative Analog Supply Current Digital Supply Current Power-Supply Rejection Ratio Shutdown Current VDD VSS VCC IDD ISS ICC PSRR Analog supply Digital supply Output unloaded, VOUT = 0 Output unloaded, VOUT = 0 All digital inputs = 0 or VCC 2.7 2.5 -0.5 9 0.001 2.8 2.8 5 5 10.80 0 5.5 8 -8 200 15.75 V V V mA mA A LSB/V A To 0.5 LSB of full scale CS = high, fSCLK = 10MHz, VOUT = 0V 2.5 10 10 2.5 130 V/s s nV-s nV-s nV/Hz SYMBOL CONDITIONS MIN TYP 10 MAX UNITS pF
MAX5322
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5
10V, Dual, 12-Bit, Serial, Voltage-Output DAC MAX5322
TIMING CHARACTERISTICS
(VDD = +15V, VSS = -15V or 0V, VCC = +2.7V to +5.5V, AGND = DGND = SGND_ = 0, VREF_ = 5V, RLOAD = 2k, ,CLOAD = 250pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SCLK Frequency SCLK Clock Period SCLK Pulse-Width High SCLK Pulse-Width Low CS Fall to SCLK Rise Setup Time SCLK Rise to CS Rise Hold Time DIN Setup Time DIN Hold Time LDAC Pulse Width CS Rise to LDAC Low Setup Time SCLK Fall to DOUT Valid Propagation Delay SCLK Rise to CS Fall Delay CS Low to DOUT Valid Time CS High to DOUT Disabled Time CS Rise to SCLK Rise Hold Time CS Pulse-Width High CLR Pulse-Width Low tCP tCH tCL tCSS tCSH tDS tDH tLD tLDS tDO1 tCS0 tCSE tCSD tCS1 tCSW tCLR +2.7V VCC +3.6V +4.5V VCC +5.5V 50 200 100 50 CLOAD = 20pF +2.7V VCC +3.6V +4.5V VCC +5.5V CLOAD = 20pF, +2.7V VCC +3.6V CLOAD = 20pF, +4.5V VCC +5.5V 10 120 120 +2.7V VCC +3.6V +4.5V VCC +5.5V For nondaisy-chain use For nondaisy-chain use For daisy-chain use 40 15 10 20 10 50 100 50 100 80 100 45 45 98 SYMBOL CONDITIONS MIN TYP MAX 10 UNITS MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note 1: Output unloaded, digital inputs = VCC or DGND. Note 2: VDD = 15.5V to 14.5V, VSS = -15.5V to -14.5V, input code = 14hex to FFFhex Note 3: Accuracy is guaranteed from code 14hex to FFFhex
6
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10V, Dual, 12-Bit, Serial, Voltage-Output DAC
Typical Operating Characteristics
(VDD = +15V, VSS = -15V for bipolar graphs, VSS = 0 for unipolar graphs, VCC = +5V, AGND = DGND = SGND_ = 0, VREF_ = +5.0V, output unloaded, TA = +25C, all graphs apply to both unipolar and bipolar, unless otherwise noted.)
INTERGRAL NONLINEARITY vs. INPUT CODE
MAX5322 toc01
MAX5322
INTEGRAL NONLINEARITY vs. REFERENCE VOLTAGE
MAX5322 toc02
DIFFERENTIAL NONLINEARITY vs. INPUT CODE
0.4 0.3 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5
MAX5322 toc03
0.5 0.4 0.3 0.2 INL (LSB)
0.5 0.4 0.3 0.2 INL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5
0.5
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 1024 2048 3072 4096 INPUT CODE (DECIMAL)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
1024
2048
3072
4096
REFERENCE VOLTAGE (V)
INPUT CODE (DECIMAL)
DIFFERENTIAL NONLINEARITY vs. REFERENCE VOLTAGE
MAX5322 toc04
BIPOLAR INL vs. TEMPERATURE
MAX5322 toc05
BIPOLAR DNL vs. TEMPERATURE
WORST CASE 0.4
MAX5322 toc06
0.5 0.4 0.3 0.2 DNL (LSB)
0.5 WORST CASE 0.4 0.3 0.2 0.1 0
0.5
0 -0.1 -0.2 -0.3 -0.4 -0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 REFERENCE VOLTAGE (V)
DNL (LSB)
INL (LSB)
0.1
0.3
0.2
0.1 -0.1 -0.2 -40 -15 10 35 60 85 TEMPERATURE (C) 0 -40 -15 10 35 60 85 TEMPERATURE (C)
UNIPOLAR SETTLING TIME (CLOAD = 250pF, RLOAD = 10k)
MAX5322 toc07
BIPOLAR SETTLING TIME (CLOAD = 250pF, RLOAD = 2k)
MAX5322 toc08
BIPOLAR MAJOR CARRY GLITCH ENERGY, CLOAD = 250pF
MAX5322 toc09
A 5V/div
CS
A 5V/div
CS
5V/div
CS
B 2V/div VOUT 0
B 5V/div VOUT 0
VOUT 100mV/div
t = 10.0s/div A: CS, 5.0V/div B: OUT, 2.0V/div A: CS, 5.0V/div B: OUT, 5.0V/div
t = 10.0s/div
t = 4.00s/div
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7
10V, Dual, 12-Bit, Serial, Voltage-Output DAC MAX5322
Typical Operating Characteristics (continued)
(VDD = +15V, VSS = -15V for bipolar graphs, VSS = 0 for unipolar graphs, VCC = +5V, AGND = DGND = SGND_ = 0, VREF_ = +5.0V, output unloaded, TA = +25C, all graphs apply to both unipolar and bipolar, unless otherwise noted.)
BIPOLAR MAJOR CARRY GLITCH CLOAD = 10pF
MAX5322 toc10
UNIPOLAR ZERO-SCALE VOLTAGE vs. TEMPERATURE
MAX5322 toc11
BIPOLAR ZERO-SCALE VOLTAGE vs. TEMPERATURE
CODE = 0X800hex
MAX5322 toc12
5V/div
CS
50 49 48 VOUT (mV)
CODE = 0X014hex
2.5
2.0
46 45 44 43 42
VOUT 100mV/div
VOUT (mV) -40 85
47
1.5
1.0
0.5
0 -15 10 35 60 -40 -15 10 35 60 85 TEMPERATURE (C) TEMPERATURE (C)
t = 4.00s/div
UNIPOLAR FULL-SCALE VOLTAGE vs. TEMPERATURE
MAX5322 toc13
POSITIVE BIPOLAR FULL-SCALE VOLTAGE vs. TEMPERATURE
MAX5322 toc14
NEGATIVE BIPOLAR FULL-SCALE VOLTAGE vs. TEMPERATURE
CODE = 0X000hex -9.993 -9.994 VOUT (V) -9.995 -9.996 -9.997 -9.998
MAX5322 toc15
10.000 9.999 9.998 VOUT (V)
9.998 9.997 9.996 VOUT (V) 9.995 9.994 9.993 9.992
-9.992
CODE = 0XFFFhex
CODE = 0XFFFhex
9.997 9.996 9.995 9.994 -40 -15 10 35 60 85 TEMPERATURE (C)
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
UNIPOLAR SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5322 toc16
BIPOLAR POSITIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX5322 toc17a
BIPOLAR NEGATIVE SUPPLY CURRENT vs. SUPPLY VOLTAGE
VDD = 15V -1
MAX5322 toc17b
5 VSS = 0V 4
5 VSS = -15V 4
0
IDD (mA)
IDD (mA)
2
2
ISS (mA) 10.8 15.8
3
3
-2
-3
1
1
-4
0 10.8 11.8 12.8 13.8 14.8 15.8 VDD (V)
0 11.8 12.8 13.8 14.8 VDD (V)
-5 -15.8 -14.8 -13.8 -12.8 -11.8 -10.8 VSS (V)
8
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10V, Dual, 12-Bit, Serial, Voltage-Output DAC
Typical Operating Characteristics (continued)
(VDD = +15V, VSS = -15V for bipolar graphs, VSS = 0 for unipolar graphs, VCC = +5V, AGND = DGND = SGND_ = 0, VREF_ = +5.0V, output unloaded, TA = +25C, all graphs apply to both unipolar and bipolar, unless otherwise noted.)
UNIPOLAR SUPPLY CURRENT vs. TEMPERATURE
4.5 4.0 3.5 IDD (mA) IDD (mA) 3.0 2.5 2.0 1.5 1.0 0.5 0 -40 -15 10 35 60 85 TEMPERATURE (C) VSS = 0V
MAX5322 toc18
MAX5322
BIPOLAR POSITIVE SUPPLY CURRENT vs. TEMPERATURE
MAX5322 toc19A
BIPOLAR NEGATIVE SUPPLY CURRENT vs. TEMPERATURE
-0.5 -1.0 -1.5 ISS (mA) -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0
MAX5322 toc19B
5.0
5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -40 -15 10 35 60
0
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
BIPOLAR SHUTDOWN CURRENT vs. TEMPERATURE
MAX5322 toc20
UNIPOLAR SHUTDOWN CURRENT vs. TEMPERATURE
MAX5322 toc21
UNIPOLAR OUTPUT VOLTAGE vs. OUTPUT CURRENT
CODE = FFFhex 10.000 9.995
MAX5322 toc22A
5 4 SHUTDOWN CURRENT (A) 3 IDD 2 1 0 -1 -2 -3 -40 -15 10 35 60 ISS ICC
5 4 SHUTDOWN CURRENT (A) 3 ICC
10.005
VOUT (V) 60 85
IDD 2 1 0 -1
9.990 9.985 9.980 9.975 9.970 9.965
85
-40
-15
10
35
9.960 0 4 8 12 16 20 IOUT (mA)
TEMPERATURE (C)
TEMPERATURE (C)
UNIPOLAR OUTPUT VOLTAGE vs. OUTPUT CURRENT
MAX5322 toc22B
BIPOLAR OUTPUT VOLTAGE vs. OUTPUT CURRENT
CODE = 000hex -9.970 -9.975 VOUT (V) VOUT (V) -9.980 -9.985 -9.990 -9.995 -10.000 -10.005
MAX5322 toc23A
BIPOLAR OUTPUT VOLTAGE vs. OUTPUT CURRENT
10.000 9.995 9.990 9.985 9.980 9.975 9.970 9.965 9.960 CODE = FFFhex
MAX5322 toc23B
0.135 0.125 0.115 0.105 VOUT (V) 0.095 0.085 0.075 0.065 0.055 0.045 0
CODE = 014hex
-9.965
10.005
0.2
0.4
0.6 IOUT (mA)
0.8
1.0
1.2
-20
-16
-12
-8
-4
0
0
4
8
12
16
20
IOUT (mA)
IOUT (mA)
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9
10V, Dual, 12-Bit, Serial, Voltage-Output DAC MAX5322
Typical Operating Characteristics (continued)
(VDD = +15V, VSS = -15V for bipolar graphs, VSS = 0 for unipolar graphs, VCC = +5V, AGND = DGND = SGND_ = 0, VREF_ = +5.0V, output unloaded, TA = +25C, all graphs apply to both unipolar and bipolar, unless otherwise noted.)
UNIPOLAR REFERENCE INPUT RESISTANCE vs. INPUT CODE
MAX5322 toc24
BIPOLAR REFERENCE INPUT RESISTANCE vs. INPUT CODE
MAX5322 toc25
UNIPOLAR REFERENCE INPUT BANDWIDTH
MAX5322 toc26
100 90 REF INPUT RESISTANCE (k) 80 70 60 50 40 30 20 10 0 0 1024 2048 3072
100 90 REF INPUT RESISTANCE (k) 80 70 60 50 40 30 20 10 0
5
0 RESPONSE (dB)
-5
-10
-15 200mVP-P INTO REF_ -20 0 1024 2048 3072 4096 0.01 0.1 1 10 100 1000 INPUT CODE (DECIMAL) FREQUENCY (kHz)
4096
INPUT CODE (DECIMAL)
BIPOLAR REFERENCE INPUT BANDWIDTH
MAX5322 toc27
UNIPOLAR STARTUP RESPONSE, CLOAD = 10pF
MAX5322 toc28A
UNIPOLAR STARTUP RESPONSE, CLOAD = 230pF
MAX5322 toc28B
5
20V/div
VDD
20V/div
VDD
0 RESPONSE (dB)
5V/div -5 5V/div -10 2V/div 200mVP-P INTO REF_ -20 0.01 0.1 1 10 100 1000
VCC
5V/div
VCC
VREF
5V/div
VREF
-15
VOUT
1V/div
VOUT
t = 10.0s/div
t = 10.0s/div
FREQUENCY (kHz)
BIPOLAR STARTUP RESPONSE, CLOAD = 10pF
MAX5322 toc29A
BIPOLAR STARTUP RESPONSE, CLOAD = 230pF
MAX5322 toc29B
20V/div
VDD
20V/div
VDD
5V/div
VCC
5V/div
VCC
10V/div
VSS
10V/div
VSS
2V/div
VOUT
1V/div
VOUT
t = 10.0s/div
t = 10.0s/div
10
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10V, Dual, 12-Bit, Serial, Voltage-Output DAC
Typical Operating Characteristics (continued)
(VDD = +15V, VSS = -15V for bipolar graphs, VSS = 0 for unipolar graphs, VCC = +5V, AGND = DGND = SGND_ = 0, VREF_ = +5.0V, output unloaded, TA = +25C, all graphs apply to both unipolar and bipolar, unless otherwise noted.)
UNIPOLAR RELEASE FROM HARDWARE SHUTDOWN RESPONSE
MAX5322 toc30
MAX5322
BIPOLAR RELEASE FROM HARDWARE SHUTDOWN RESPONSE
MAX5322 toc31
UNIPOLAR SOFTWARE-SHUTDOWN RESPONSE
MAX5322 toc32A
VOUT VOUT 5V/div 5V/div
5V/div
CS
VSHDN
VSHDN 5V/div VOUT
2V/div
2V/div
t = 100s/div
t = 100s/div
t = 40.0s/div
BIPOLAR SOFTWARE-SHUTDOWN RESPONSE
MAX5322 toc32B
DAC-TO-DAC CROSSTALK
MAX5322 toc33
5V/div
CS OUTB
1mV/div 0V
5V/div 10V/div VOUT OUTA 0V
t = 40.0s/div
t = 100s/div
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11
10V, Dual, 12-Bit, Serial, Voltage-Output DAC MAX5322
Pin Description
PIN 1, 2, 13-16, 27, 28 3 NAME N.C. No Connection. Not internally connected. DAC B Output-Mode Selection Input. Selects unipolar or bipolar output. Logic high = unipolar, logic low = bipolar. In unipolar mode, the analog output range is 0 to 2 x VREF. In bipolar mode, the analog output range is (-2 x VREF) to (+2 x VREF). Active-Low Shutdown Input. Pulling SHDN low forces the DAC buffers into high impedance. Drive SHDN high for normal operation. Active-Low Load DAC Input. DAC A and DAC B are updated with information in the input register on the LDAC falling edge. Active-Low Asynchronous Clear DAC Input. Pulling CLR low clears all DACs and input registers; resets all outputs to zero. Digital Ground Digital Power Input. Connect VCC to a +2.7V to +5.5V power supply. Bypass VCC to DGND with a 10F and 0.1F capacitor in parallel as close to the device as possible. Serial-Data Output. Data is clocked out on SCLK's falling edge. DOUT is high impedance when CS is high. Data shifted into DIN appears at DOUT 16.5 clock cycles later. Serial-Clock Input. SCLK clocks data in and out of the serial interface. Serial-Data Input. Data is clocked in on the rising edge of SCLK. Active-Low Chip-Select Input. Data is not clocked into DIN unless CS is low. DAC A Output-Mode Selection. Selects unipolar or bipolar output. Logic high = unipolar, logic low = bipolar. In unipolar mode, the analog output range is 0 to 2 x VREF. In bipolar mode, the analog output range is (-2 x VREF) to (+2 x VREF). DAC A Output DAC A Sense Ground. Connect to AGND. Reference Input for DAC A Positive Analog-Power Input. Connect VDD to a +10.8V to +15.75V power supply. Bypass VDD to AGND with a 10F and 0.1F capacitor in parallel as close to the device as possible. DAC B Reference Input Analog Ground DAC B Sense Ground. Connect to AGND. DAC B Output Negative Analog-Power Input. For single-supply operation, connect VSS to AGND. For dual-supply operation, connect VSS to a -10.8V to -15.75V power supply and bypass VSS to AGND with a 10F and 0.1F capacitor in parallel, as close to the device as possible. FUNCTION
UNI/BIPB
4 5 6 7 8 9 10 11 12 17 18 19 20 21 22 23 24 25 26
SHDN LDAC CLR DGND VCC DOUT SCLK DIN CS UNI/BIPA OUTA SGNDA REFA VDD REFB AGND SGNDB OUTB VSS
12
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10V, Dual, 12-Bit, Serial, Voltage-Output DAC
Detailed Description
The MAX5322 dual, 12-bit DAC operates from either single or dual analog supplies. Dual 12V to 15V power supplies provide bipolar 5V to 10V outputs, or unipolar 0V to 10V outputs. Single 12V to 15V analog power supplies only provide unipolar 0 to 10V outputs. The reference inputs accept voltages from 2V to 5.25V. The DAC features INL and DNL less than 1 LSB (max), a fast 10s settling time, and a hardware shutdown mode that reduces current consumption to 2.8A. The device features a 10MHz SPI-/QSPI-/MICROWIRE-compatible serial interface that operates with 3V or 5V logic, an asynchronous load input, and a serial-data output. The device offers a CLR that sets the DAC outputs to 0V. Figure 1 shows the functional diagram of the MAX5322.
Serial Interface
An SPI-/QSPI-/MICROWIRE-compatible serial interface allows complete control of the DAC through a 16-bit control word. The first 4 bits form the control bits that determine register loading and software shutdown functions. The last 12 bits form the DAC data. The 16bit word is entered MSB first. Table 1 shows the serial-data control-word format. Table 2 shows the interface commands. The MAX5322 can be programmed while in shutdown. The serial interface contains five registers: a 16-bit shift register, two 12-bit input registers, and two 12-bit DAC registers (Figure 1). The shift register accepts data from the serial interface. The input registers act as holding registers for data going to the DAC registers
MAX5322
Table 1. Control-Word Format
CONTROL BITS MSB C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DATA BITS LSB D0
Table 2. Serial-Interface Programming Commands
16-BIT SERIAL WORD CONTROL BITS C3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 C2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 C1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 C0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DATA BITS D11-D0 XXXXXXXXXXXX 12-bit DAC data 12-bit DAC data 12-bit DAC data 12-bit DAC data 12-bit DAC data XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX No operation (NOP). Load both DAC registers and both input registers from the shift register. (Start both DACs with new data.) Load input register A from the shift register; DAC registers are unchanged. Load input register B from the shift register; DAC registers are unchanged. Load DAC register A and input register A from the shift register. Load DAC register B and input register B from the shift register. Update DAC register A from input register A (no data sent). Update DAC register B from input register B (no data sent). Shut down DAC A (provided SHDN = 1). Shut down DAC B (provided SHDN = 1). Update both DAC registers from their respective input registers. (Start both DACs with data previously stored in the input register.) Shut down both DACs (provided SHDN = 1). Power up DAC A (no change to any registers). Power up DAC B (no change to any registers). Power up both DACs (no change to any registers). Not used. FUNCTION
X = Don't care. Note: The DACs can be programmed in shutdown mode.
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13
10V, Dual, 12-Bit, Serial, Voltage-Output DAC
and isolate the shift register from the DAC registers. The DAC registers control the DAC ladder and thus the output voltage. Any update to a DAC register updates the respective output voltage. Data in the shift register is transferred to the input registers during the appropriate software command only. Data in the input registers is transferred to the DAC registers in two ways: using the software command, or through external logic control using the asynchronous load input (LDAC). Table 2 shows the software commands that transfer the data from the shift register to the input and/or DAC registers. The CLR, an external logic control, asynchronously forces all outputs to 0V, in both unipolar and bipolar modes. Interface timing is shown in Figures 2 and 3. Wait a minimum of 100ns after CS goes high before implementing LDAC or CLR. If either of these logic inputs activates during a data transfer, the incoming data is corrupted and needs to be reloaded. For software control only, tie LDAC and CLR high.
MAX5322
DAC Architecture
The MAX5322 uses an inverted DAC ladder architecture to convert the digital input into an analog output voltage. The digital input controls weighted switches that connect the DAC-ladder nodes to either REFA (REFB) or GND (Figure 4). The sum of the weights produces the analog equivalent of the digital-input word and is then buffered at the output.
External Reference and Transfer Functions
Connect an external reference of 2V to 5.25V to REFA and REFB. Set the output voltage range with the reference and the input code by using the equations below. Unipolar output voltage: VOUT _ UNI = LSBUNI x CODE
CS
COMMAND EXECUTED
SCLK 1 DIN C3 C2 C1 C0 D11 D10 D9 8 D8 D7 9 D6 D5 D4 D3 D2 D1 16 D0 (1)
Figure 2. Serial-Interface Signals
tCSW CS tCS0 SCLK tCH tDS DIN tCSE DOUT tLDS tLD LDAC MSB tDO1 tDH LSB tCSD tCL tCSS tCP tCSH tCS1
Figure 3. Serial-Interface Timing Diagram 14 ______________________________________________________________________________________
10V, Dual, 12-Bit, Serial, Voltage-Output DAC
where: LSBUNI = Bipolar output voltage: VOUT _ BIP = (LSBBIP x CODE) - (2 x VREF ) where: LSBBIP = 4 x VREF 212 2 x VREF 212 This configuration channels the DAC output through two output stages to generate the 2 x VREF output swing. The first amplifier generates the VREF voltage range and the second amplifier gains it up by two. When configured for bipolar operation, the MAX5322 must be driven with dual 12V to 15V power supplies. With UNI/BIPA (UNI/BIPB) forced high, switches SW1 (SW4) and SW2 (SW5) are open and SW3 (SW6) is closed. This configuration channels the DAC output through only a single gain stage to generate a 0 to 2 x VREF output swing. Daisy-Chaining SPI-/QSPI-/MICROWIRE-compatible devices can be daisy-chained to reduce I/O lines from the host controller (Figure 7). Daisy-chain devices by connecting the DOUT of one device to the DIN of the next, and connect the SCLK of all devices to a common clock. Data is shifted out of DOUT 16.5 clock cycles after it is shifted into DIN, and is available on the rising edge of the 17th clock cycle. The SPI-/QSPI-/MICROWIRE-compatible serial interface normally works at up to 10MHz, but must be slowed to 6MHz if daisy-chaining. DOUT is high impedance when CS is high.
MAX5322
where VOUT_UNI is the unipolar output voltage, VOUT_BIP is the bipolar output voltage, LSBUNI is the unipolar LSB step size, LSBBIP is the bipolar LSB step size, VREF is the reference voltage, and CODE is the decimal equivalent of the binary, 12-bit, DAC input code. In either case, a 000hex input code produces the minimum output (-2 x VREF for bipolar and zero for unipolar), an 800hex input code produces the midscale output (zero for bipolar and VREF for unipolar), and a FFFhex input code produces the full-scale output (2 x VREF for bipolar and unipolar).
Shutdown
Shutdown is controlled by software commands or by the SHDN logic input. The SHDN logic input may be implemented at any time. The SPI-/QSPI-/MICROWIRE-compatible serial interface remains fully functional, and the device is programmable while shutdown. When shut down, the MAX5322 supply current reduces to 2.8A
2R
Output Amplifiers
The output-amplifier section can be configured as either unipolar or bipolar by the UNI/BIP logic input. With UNI/BIPA (UNI/BIPB) forced low, SW1 (SW4) and SW2 (SW5) in Figure 1 are closed, and SW3 (SW6) is open.
2R
R
R
R
MAX5322
SW2 2R 2R 2R 2R 2R SW1 OUTA D0 1 REFA AGND 2R SGNDA DAC REGISTER A 0 1 D1 0 1 D10 0 1 D11 0 SW3 2R
UNI/BIPA
CONTROL LOGIC
Figure 4. Basic Inverted DAC Ladder ______________________________________________________________________________________ 15
10V, Dual, 12-Bit, Serial, Voltage-Output DAC MAX5322
(max), DOUT is high impedance, and OUTA and OUTB are pulled to SGNDA and SGNDB, respectively, through the internal feedback resistors of the output amplifier (Figure 1). When coming out of shutdown, or during device power-up, allow 350s for the output to stabilize.
Power-Supply Bypassing and Ground Management
Bypass VDD and VSS with 1.0F and 0.1F capacitors to AGND, and bypass VCC with a 1.0F and 0.1F capacitors to DGND. Minimize trace lengths to reduce inductance. Digital and AC transient signals on AGND or DGND can create noise at the output. Connect AGND and DGND to the highest quality ground available. Use proper grounding techniques, such as a multilayer board with a low-inductance ground plane or star connect all ground return paths back to AGND. Carefully lay out the traces between channels to reduce AC cross coupling and crosstalk. Wire-wrapped boards, sockets, and breadboards are not recommended.
Applications Information
Power Supplies
A single supply of +12V to +15V is required to realize an output swing of 0 to 10V. A dual supply of 12V to 15V is required to realize an output swing of 10V, and allows unipolar, 0 to +10V output if UNI/BIP_ is forced high. A +3V to +5V digital power supply and two +2.000V to +5.250V external reference voltages are also required. Always bring up the reference voltages last; the other power supplies do not require sequencing.
Table 3. Output Voltage as Input Code Examples
BINARY DAC CODE MSB LSB UNIPOLAR (UNI/BIP_ = HIGH) +2 x VREF (4095 / 4096) +2 x VREF (2049 / 4096) +2 x VREF (2048 / 4096) = VREF +2 x VREF (2047 / 4096) +2 x VREF (1 / 4096) 0 1111 1111 1111 1000 0000 0001 1000 0000 0000 0111 1111 1111 0000 0000 0001 0000 0000 0000 ANALOG OUTPUT BIPOLAR (UNI/BIP_ = LOW) +2 x VREF (2047 / 2048) +2 x VREF (1 / 2048) 0 -2 x VREF (1 / 2048) -2 x VREF (2047 / 2048) -2 x VREF (2048 / 2048) = -2 x VREF
1 LSB = 4095 4094 4093 4092
2 x VREF 4096 +2047 +2046 +2045 +2044
1 LSB =
4 x VREF 4096
ANALOG OUTPUT VOLTAGE (LSB)
ANALOG OUTPUT VOLTAGE (LSB)
2049 2048 2047
+1 0 -1
2 x VREF
3 2 1 0 FFC FFD FFE FFF 000 001 002 003 7FF 800 801 hex DIGITAL INPUT CODE (LSB)
-2045 -2046 -2047 -2048 hex DIGITAL INPUT CODE (LSB) FFC FFD FFE FFF 000 001 002 003 7FF 800 801
Figure 5. Unipolar Transfer Function 16
Figure 6. Bipolar Transfer Function
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4 x VREF
10V, Dual, 12-Bit, Serial, Voltage-Output DAC MAX5322
SCLK CS CS CS CS TO OTHER SERIAL DEVICES
MAX5322
SCLK SCLK
MAX5322
SCLK
MAX5322
DIN
DIN
DOUT
DIN
DOUT
DIN
DOUT
Figure 7. Daisy-Chaining Devices
Pin Configuration
TOP VIEW
N.C. 1 N.C. 2 UNI/BIPB 3 SHDN 4 LDAC 5 CLR 6 DGND 7 VCC 8 DOUT 9 SCLK 10 DIN 11 CS 12 N.C. 13 N.C. 14 28 N.C. 27 N.C. 26 VSS 25 OUTB 24 SGNDB
Chip Information
TRANSISTOR COUNT: 5914 PROCESS: BiCMOS
MAX5322
23 AGND 22 REFB 21 VDD 20 REFA 19 SGNDA 18 OUTA 17 UNI/BIPA 16 N.C. 15 N.C.
SSOP
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17
10V, Dual, 12-Bit, Serial, Voltage-Output DAC MAX5322
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
2
1
INCHES DIM A A1 B C E H D E e H L MIN 0.068 0.002 0.010 MAX 0.078 0.008 0.015
MILLIMETERS MIN 1.73 0.05 0.25 MAX 1.99 0.21 0.38 D D D D D INCHES MIN 0.239 0.239 0.278 0.317 0.397 MAX 0.249 0.249 0.289 0.328 0.407 MILLIMETERS MIN 6.07 6.07 7.07 8.07 10.07 MAX 6.33 6.33 7.33 8.33 10.33 N 14L 16L 20L 24L 28L
0.20 0.09 0.004 0.008 SEE VARIATIONS 0.205 0.301 0.025 0 0.212 0.311 0.037 8 5.20 7.65 0.63 0 5.38 7.90 0.95 8 0.0256 BSC 0.65 BSC
N
A C B e D A1 L
NOTES: 1. D&E DO NOT INCLUDE MOLD FLASH. 2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED .15 MM (.006"). 3. CONTROLLING DIMENSION: MILLIMETERS. 4. MEETS JEDEC MO150. 5. LEADS TO BE COPLANAR WITHIN 0.10 MM.
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, SSOP, 5.3 MM
APPROVAL DOCUMENT CONTROL NO. REV.
21-0056
1 1
C
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.
SSOP.EPS

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